H7068 DIGITAL SYSTEMS AND MICROPROCESSOR DESIGN: COURSEWORK RETAKE
2021/22
Remarks:
All the coursework has to be done in VHDL. Coursework handed in using another language will be
marked as zero.
Coursework must be typeset.
Never use screenshots or photograph of code in your coursework. Typeset code within your
coursework report using a monospace font (e.g. courier new).
Never use photographs of waveforms in your coursework. Use a proper screen capture tool to include
a high resolution screenshot in your coursework.
The FPGA board is not required for this coursework
Vivado is not necessary for this coursework (syntax errors will not penalise the evaluation).
a) Consider the following DFF with active high enable, asynchronous active high reset,
synchronous active high set, and reacting on the falling edge of the clock (D, E, Clk, Q, S, R
are all std_logic):
Write the VHDL code for this component and explain your implementation.
[20 marks for the DFF complete source and explanations]
b) Write a testbench to simulate the DFF of question a. Make sure all the relevant conditions
are tested. In the report:
i) Provide the code of the testbench and explain your testbench
ii) Indicate for each condition what is the expected outcome if the DFF were operating
correctly.
[20 marks for the testbench complete source, explanations and expected results]
c) Consider an input signal coming from a digital microphone in “pulse density modulation”
(see here for details: https://en.wikipedia.org/wiki/Pulse-density_modulation).
A PDM signal is a sequence of 1 and 0s updated following the rising edge of a clock signal.
The number of 1s over the last N clock cycles (window size) represents the decimal value of
the signal. This value ranges from 0 (the PDM signal was 0 during the last N clock cycles) to
N (the PDM signal was 1 during the last N clock cycles).
The following figure illustrates this with a window size N=4. The output value is updated on
the rising edge of the clock. In order to make the figure more legible, we show the output
value updated a very short time after the rising edge of the clock.
H7068 DIGITAL SYSTEMS AND MICROPROCESSOR DESIGN: COURSEWORK RETAKE
2021/22
We are interested in a software and a hardware approach to decode the incoming PDM
signal into a decimal value.
The software approach consists of a program running on the UoS educational processor.
The software will continuously generate the clk signal, read in the pdm signal, and compute
the value, using a window of N=4 clock cycles, as illustrated above.
The software generates the clk signal using the bit 0 of the external output of the
processor. This is done using the “out” instruction. This instruction has not been used in the
lab if you studied in 2020, however it works as follows: out 0 sets the clock to 0; out 1
sets the clock to 1.
The software reads the pdm signal on the bit 0 of the external input. The external input is
read with the “in” instruction. This instruction has not been used in the lab if you studied in
2021, however it works as follows: in RD reads the external input and stores it in register
RD. You can assume that the bits 7…1 are always 0, and the LSB of RD indicates if the input
is 1 or 0.
The resulting value must be stored in a register or memory location of your choosing. There
is no need to guarantee a particular frequency or duty cycle of clk in this coursework.
The hardware approach consists of realising a digital circuit (represented as a schematic,
not VHDL, for simplicity reasons) which converts a PDM input into a value output, using a
window of N=4 clock cycles, as illustrated above. In this hardware implementation, assume
the inputs of the circuit are clk and pdm (std_logic) and the output is value
(std_logic_vector(3 downto 0)). I.e., the clock is provided to your circuit by some
external system.
In the report:
i) Realise a program to implement the software approach. Provide the assembler code,
and explanations of how the program works. Make sure you explain where the resulting
value is available (e.g. in which register).
ii) Realise the hardware approach by presenting a schematic of a digital circuit realizing the
desired function. Provide a schematic of the circuit, and explanation of how the circuit works.
H7068 DIGITAL SYSTEMS AND MICROPROCESSOR DESIGN: COURSEWORK RETAKE
2021/22
iii) Discuss the advantages and disadvantages of each approach.
[40 marks (15 marks per implementation with comments, 10 mark for the indentification of
advantages and disadvantages]
d) The Sussex Educational Processor executes an instruction every 3 clock cycles. Explain
why that is the case and specifically what happens during each of these three clock cycles.
[10 marks]
e) Explain the possible reasons why two’s complement is the most commonly used
representation for negative numbers in digital circuits and especially computer systems.
[10 marks]
Please refer to your own Assessment Deadlines & Exam Timetable in Sussex Direct for all submission
details
