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Your mission: Design a simplified Kalman filter in a VHDL module.
A data stream of bytes is being received synchronous to the local system clock: 10 megabytes/sec, as unsigned bytes. With each new datum, the filter must: 1) Compute the weighted average of the previous 3 samples and the current sample before the next clock edge. The result is a Moore output with no glitches. 2) The four samples are weighted 4, 2, 1, 1. I.e. let s(3) be the current sample, s(0) the oldest, Output = ? ( 4 * sample (3) + 2 * sample (2) + sample (1) + sample (0) ) div 8.3) Multiplication and division is intentionally a power of 2 to enable calculation by shifting bits.4) When the next datum arrives, sample (0) <= sample (1), sample (1) <= sample (2), sample (2) <= sample (3), sample (3) <= new_datum and the process repeats.? Create the VHDL module by first creating a state chart with RTL notation. ? Speed of calculation is the prime mission; register / logic minimization is not the mission. ? Accomplish the multiplication and division by bit shifting e.g. using the sll operation. Notes:? Use type unsigned for the sample values. For convenience, create an array of unsigned. Specify a range that covers at least byte values * 8 to preclude overflow / carry events.? At each clock edge, the first process step is to capture the previous calculated output value into an output register, so the clock can be as fast as possible yet provide a Moore output. ? The calculation should be accomplished in combinatorial logic. Ergo the next process step is to shift register contents (sample (0) <= sample (1), etc.) and capture the new datum. The result of the combinatorial calculation is awaiting capture in a register at the next clock. Estimate the minimum clock period for this filter: shifts take 10 ns, addition takes 25 ns. Be sure to consider what operations occur simultaneously. A timing diagram will be useful.
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